Secure decryption algorithms are a type of cryptographic algorithms whose importance in today's society has been highlighted by applications such as the use of personal digital tools to maintain confidentiality. On the other hand, with the advancement of technology, the More
Secure decryption algorithms are a type of cryptographic algorithms whose importance in today's society has been highlighted by applications such as the use of personal digital tools to maintain confidentiality. On the other hand, with the advancement of technology, the need to implement these algorithms on flexible platforms can be challenging. Reducing the area and speeding up the execution of operations are the main challenges for designing and implementing these algorithms. This paper proposes a new architecture for the FPGA-based processor for SHA-2 series cryptographic algorithms. In the proposed processor, the use of memory units and multi-port data path, followed by parallel processor performance, has reduced the use of resources and increased the speed of data processing. Processor architecture for SHA-2 cryptographic algorithms is modeled in VHDL and implemented on the FPGA platform in the Virtex series by ISE software. Implementation results show that the proposed compact processor compared to previous tasks with similar objectives, was able to increase the operating frequency for the SHA-256 cryptographic algorithm by 25% and occupy 55% less space for the SHA-512 cryptographic algorithm to the desired level of operational power and efficiency. Also maintain. The proposed processor is suitable for applications such as trusted mobile platforms (TMP), digital currency (Bitcoin) and secure on-chip network routing (NoC).
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